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MC74HC161A, MC74HC163A Presettable Counters
High-Performance Silicon-Gate CMOS
The MC74HC161A and HC163A are identical in pinout to the LS161 and LS163. The device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. The HC161A and HC163A are programmable 4-bit binary counters with asynchronous and synchronous reset, respectively.
http://onsemi.com MARKING DIAGRAMS
16
16 1
* * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 192 FETs or 48 Equivalent Gates
MC74HC16xAN AWLYYWW 1
PDIP-16 N SUFFIX CASE 648
16
16 1
HC16xA AWLYWW 1
RESET CLOCK P0 P1 P2 P3 ENABLE P GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC RIPPLE CARRY OUT Q0 Q1 Q2 Q3 ENABLE T LOAD
SO-16 D SUFFIX CASE 751B
16
16 1
TSSOP-16 DT SUFFIX CASE 948F
HC 16xA ALYW 1
Figure 1. Pin Assignment
x A L, WL Y, YY W, WW
= 1 or 3 = Assembly Location = Wafer Lot = Year = Work Week
FUNCTION TABLE
Inputs Clock Reset* L H H H H Load X L H H H Enable P X X H L X Enable T X X H X L Output Q Reset Load Preset Data Count No Count No Count
ORDERING INFORMATION
Device MC74HC161AN MC74HC161AD MC74HC161ADR2 MC74HC161ADT MC74HC161ADTR2 MC74HC163AN MC74HC163AD MC74HC163ADR2 MC74HC163ADT MC74HC163ADTR2 Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 2000/Box 48/Rail 2500/Reel 96/Rail 2500/Reel 2000/Box 48/Rail 2500/Reel 96/Rail 2500/Reel
*HC163A only. HC161A is an Asynchronous Reset Device H = high level, L = low level, X = don't care
(c) Semiconductor Components Industries, LLC, 2001
1
June, 2001 - Rev. 9
Publication Order Number: MC74HC161A/D
MC74HC161A, MC74HC163A
3 4 5 6 14 13 12 11
P0 PRESET DATA INPUTS P1 P2 P3
Q0 Q1 Q2 Q3 RIPPLE CARRY OUT BCD OR BINARY OUTPUT
CLOCK
2
15
RESET LOAD COUNT ENABLES ENABLE P ENABLE T
1 9 7 10 PIN 16 = VCC PIN 8 = GND
Figure 2. Logic Diagram
IIIIIIIIIII II IIIIIIIIIII IIIII I II I II II I IIIIIIIIIII IIIIIIIIIII IIIIIIIIII III I IIIIIIIIIII IIIIIIIIIII IIIIII IIIIIIIIIII
DEVICE/MODE TABLE
Count Mode Binary Binary Device Reset Mode HC161A HC163A Asynchronous Synchronous
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MC74HC161A, MC74HC163A
MAXIMUM RATINGS (Note 1.)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance PDIP SOIC TSSOP PDIP SOIC TSSOP (Note 2.) Parameter Value *0.5 to )7.0 *0.5 to VCC )0.5 *0.5 v VO v VCC )0.5 $20 $25 $25 $50 $50 *65 to )150 260 )150 78 112 148 750 500 450 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 3.) Machine Model (Note 4.) Charged Device Model (Note 5.) Above VCC and Below GND at 85_C (Note 6.) UL-94-VO (0.125 in) u2000 u200 u1000 $300 V Unit V V V mA mA mA mA mA _C _C _C _C/W
PD
Power Dissipation in Still Air at 85_C
mW
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
ILATCH-UP
Latch-Up Performance
mA
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. 2. IO absolute maximum rating must be observed. 3. Tested to EIA/JESD22-A114-A. 4. Tested to EIA/JESD22-A115-A. 5. Tested to JESD22-C101-A. 6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC DC Supply Voltage Parameter (Referenced to GND) Min 2.0 0 Max 6.0 Unit V V
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Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) VCC Operating Temperature, All Package Types Input Rise and Fall Time (Figure 4) *55 0 0 0 0 )125 1000 600 500 400 _C ns tr, tf VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V 7. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level.
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3
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8. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ICC
Iin
VOL
VOH
VIL
VIH
Symbol
Maximum Quiescent Supply Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Vin = VIH or VIL |Iout| v 20 mA
Vin = VIH or VIL |Iout| v 20 mA
Vin = VCC or GND Iout = 0 mA
Vin = VCC or GND
Vin = VIH or VIL |Iout| v 3.6 mA |Iout| v 4.0 mA |Iout| v 5.2 mA
Vin = VIH or VIL |Iout| v 3.6 mA |Iout| v 4.0 mA |Iout| v 5.2 mA
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
MC74HC161A, MC74HC163A
Test Conditions
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VCC V 6.0 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -55 to 25_C 0.1 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.26 0.26 0.26 2.48 3.98 5.48 4.0 0.1 0.1 0.1 1.9 4.4 5.9 Guaranteed Limit v 85_C 1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.33 0.33 0.33 2.34 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 40 v 125_C 1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 160 0.4 0.4 0.4 0.1 0.1 0.1 2.2 3.7 5.2 1.9 4.4 5.9 Unit mA mA V V V V
4
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol Cin tTLH, tTHL tPHL tPHL tPLH tPHL tPLH tPHL tPHL tPLH fmax Maximum Input Capacitance Maximum Output Transition Time, Any Output Maximum Propagation Delay, Reset to Ripple Carry Out (HC161A Only) Maximum Propagation Delay, Clock to Ripple Carry Out Maximum Propagation Delay, Enable T to Ripple Carry Out Maximum Propagation Delay, Reset to Q (HC161A Only) Maximum Propagation Delay, Clock to Q Maximum Clock Frequency (50% Duty Cycle) (Note 9.) Parameter
10. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
45 CPD Power Dissipation Capacitance (Per Gate) (Note 11.) pF 11. Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
9. Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However, if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable. See Applications information in this data sheet.
MC74HC161A, MC74HC163A
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Figure 4, 10 5, 10 5, 10 4, 10 4, 10 6, 10 6, 10 5, 10 4, 10 4, 10 4, 10 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C 155 120 22 18 145 100 22 20 120 75 22 18 135 100 18 15 145 100 20 17 145 100 22 18 120 75 20 16 110 60 16 14 6 15 30 35 10 75 30 15 13 Typical @ 25C, VCC = 5.0 V Guaranteed Limit v 85_C 190 140 26 22 185 135 28 24 160 135 27 22 175 130 20 16 150 115 18 15 185 135 22 19 185 135 25 20 160 120 23 20 5 12 24 28 10 95 40 19 16 v 125_C 230 155 30 25 220 150 35 28 200 150 30 25 210 160 22 20 190 140 20 17 220 150 25 21 220 150 30 23 200 150 28 22 110 55 22 19 4 10 20 24 10 MHz Unit pF ns ns ns ns ns ns ns ns ns
5
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TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tr, tf tw tw trec trec th th th tsu tsu tsu tsu Maximum Input Rise and Fall Times Minimum Pulse Width, Reset (HC161A Only) Minimum Pulse Width, Clock Minimum Recovery Time, Load Inactive to Clock Minimum Recovery Time, Reset Inactive to Clock (HC161A Only) Minimum Hold Time, Clock to Enable T or Enable P Minimum Hold Time, Clock to Reset (HC163A Only) Minimum Hold Time, Clock to Load or Preset Data Inputs Minimum Setup Time, Enable T or Enable P to Clock Minimum Setup Time, Reset to Clock (HC163A Only) Minimum Setup Time, Load to Clock Minimum Setup Time, Preset Data Inputs to Clock Parameter
MC74HC161A, MC74HC163A
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Figure 5 4 8 5 9 7 8 9 7 8 8 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 60 25 12 10 60 25 12 10 80 35 15 12 80 35 15 12 80 35 20 17 60 25 20 17 60 25 15 12 40 20 15 12 3 3 3 3 3 3 3 3 3 3 3 3 Guaranteed Limit v 85_C 1000 800 500 400 75 30 15 13 75 30 15 13 95 40 20 17 95 40 20 17 95 40 25 23 75 30 25 23 75 30 20 18 60 30 20 18 3 3 3 3 3 3 3 3 3 3 3 3 v 125_C 1000 800 500 400 110 50 26 23 110 50 26 23 110 50 35 25 90 40 18 15 90 40 18 15 90 40 35 25 90 40 30 20 80 40 30 20 3 3 3 3 3 3 3 3 3 3 3 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns
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MC74HC161A, MC74HC163A
FUNCTION DESCRIPTION The HC161A/163A are programmable 4-bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading, and count-enable controls. The HC161A and HC163A are binary counters with asynchronous Reset and synchronous Reset, respectively.
INPUTS Clock (Pin 2) CONTROL FUNCTIONS Resetting
A low level on the Reset pin (Pin 1) resets the internal flip-flops and sets the outputs (Q0 through Q3) to a low level. The HC161A resets asynchronously, and the HC163A resets with the rising edge of the Clock input (synchronous reset).
Loading
The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting and loading, occur with the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
With the rising edge of the Clock, a low level on Load (Pin 9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flip-flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low.
Count Enable/Disable
These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. P0 (Pin 3) is the least-significant bit and P3 (Pin 6) is the most-significant bit.
OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These devices have two count-enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count when these two pins and the Load pin are high. The logic equation is:
Count Enable = Enable P * Enable T * Load
These are the counter outputs. Q0 (Pin 14) is the least-significant bit and Q3 (Pin 11) is the most-significant bit.
Ripple Carry Out (Pin 15)
The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count-enable control: Enable T is both a count-enable and a Ripple-Carry Output control.
Table 1. Count Enable/Disable
Control Inputs Load H L X X Enable P H H L X Enable T H H H L Result at Outputs Q0 - Q3 Count No Count No Count No Count High when Q0 Q3 Q0-Q3 are maximum* High when Q0-Q3 are maximum* L Ripple Carry Out
When the counter is in its maximum state, 1111, this output goes high, providing an external look-ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is:
Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3
OUTPUT STATE DIAGRAMS
0 1 2 3 4
*Q0 through Q3 are maximum when Q3, Q2, Q1, Q0 = 1111.
15
5
14
6
13
7
12
11
10
9
8
Figure 3. Binary Counters
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MC74HC161A, MC74HC163A
SWITCHING WAVEFORMS
tr 90% 50% 10% tw 1/fmax tPLH tPHL ANY OUTPUT 90% 50% 10% tTLH tTHL ANY OUTPUT CLOCK tf tw VCC RESET tPHL 50% trec VCC 50% GND 50% GND
VCC GND
CLOCK
Figure 4.
Figure 5.
tr ENABLE T 90% 50% 10%
tf VCC GND tPHL CLOCK tTHL tsu th VCC 50% GND RESET 50%
tPLH 90% RIPPLE 50% CARRY 10% OUT tTLH
Figure 6.
Figure 7. HC163A Only
VALID INPUTS P0, P1, P2, P3 VCC 50% GND tsu LOAD 50% GND tsu CLOCK th 50% GND trec VCC CLOCK th VCC ENABLE T OR ENABLE P 50% GND tsu th VCC 50% GND VALID VCC
Figure 8.
Figure 9.
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
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8
P0
3
T0 R Q0 C C LOAD LOAD Q0 P0
14
Q0
Figure 11. 4-Bit Binary Counter with Asynchronous Reset (MC74HC161A)
P1 4
T1 Q1 R C C LOAD LOAD Q1 P1 T2 R Q2 C C LOAD LOAD Q2 P2
13
Q1
MC74HC161A, MC74HC163A
12
Q2
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P2
5
9
P3
6
T3 R Q3 C C LOAD LOAD P3
11
Q3
ENABLE P
7 VCC= PIN 16 GND = PIN 8 R LOAD LOAD 2 C C
15 RIPPLE CARRY OUT
ENABLE T RESET
10 1
LOAD CLOCK
9
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
MC74HC161A, MC74HC163A
Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one and two. 4. Inhibit. RESET (HC161A) RESET (HC163A) LOAD
(ASYNCHRONOUS) (SYNCHRONOUS)
P0 PRESET DATA INPUTS P1 P2 P3 CLOCK (HC161A) CLOCK (HC163A)
COUNT ENABLES
ENABLE P ENABLE T Q0 Q1
OUTPUTS Q2 Q3 RIPPLE CARRY OUT RESET
12 LOAD
13 14
15
0
1
2 INHIBIT
COUNT
Figure 12. Timing Diagram
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10
P0
3
T0 R Q0 C C LOAD LOAD Q0 P0
14
Q0
Figure 13. 4-Bit Binary Counter with Synchronous Reset (MC74HC163A)
P1
4
T1 Q1 R C C LOAD LOAD Q1 P1 T2 R Q2 C C LOAD LOAD Q2 P2
13
Q1
MC74HC161A, MC74HC163A
12
Q2
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P2
5
11
P3
6
T3 R Q3 C C LOAD LOAD P3
11
Q3
ENABLE P
7 VCC= PIN 16 GND = PIN 8 R LOAD LOAD 2 C C
15 RIPPLE CARRY OUT
10 ENABLE T RESET 1
LOAD CLOCK
9
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD INPUTS INPUTS INPUTS
LOAD P0 P1 P2 P3 H = COUNT L = DISABLE H = COUNT L = DISABLE ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R RESET OUTPUTS CLOCK Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3 TO MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Figure 14. N-Bit Synchronous Counters
INPUTS
INPUTS
INPUTS
LOAD ENABLE P ENABLE T LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK CLOCK R RESET Q0 Q1 Q2 Q3 LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3 LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3 TO MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
OUTPUTS
Figure 15. Nibble Ripple Counter http://onsemi.com
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MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HC163A OTHER Q0 INPUTS Q1 Q2 Q3 OPTIONAL BUFFER FOR NOISE REJECTION
HC163A OTHER Q0 INPUTS Q1 Q2 Q3 RESET OPTIONAL BUFFER FOR NOISE REJECTION OUTPUT
OUTPUT
RESET
Figure 16. Modulo-5 Counter
Figure 17. Modulo-11 Counter
The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous Reset.
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13
MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
D SUFFIX SOIC CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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15
EEE CCC EEE CCC
-W-
MC74HC161A, MC74HC163A
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC74HC161A/D

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